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up1965s 1 up1965s-ds-f0000, may. 2018 www.upi-semi.com 5v mosfet driver with output disable for single phase synchronous-rectified buck converter ?? ?? ? single 5v driving voltage output ?? ?? ? integrated bootstrap diode ?? ?? ? integrated gate-to-source discharge resistors ?? ?? ? enable/disable control ?? ?? ? allow pwm pin as multi-function setting application ?? ?? ? three pwm input states: high, low and tri-state ?? ?? ? tri-state input for bridge shutdown ?? ?? ? anti-shoot-through protection circuitry ?? ?? ? under voltage lockout for supply input ?? ?? ? wdfn2x2-8l package ?? ?? ? rohs compliant and halogen free rebmunredr oe gakca pg nikram pot 8nds5691p ul 8-2x2nfd wf h general description applications ordering information features note: (1) please check the sample/production availability with upi representatives. (2) upi products are compatible with the current ipc/ jedec j-std-020 requirements. they are halogen-free, rohs compliant and 100% matte tin (sn) plating that are suitable for use in snpb or pb-free soldering processes. the up1965s is 5v mosfet driver optimized for driving two n-channel mosfets in a synchronous rectified buck converter for mobile computing application. this part has integrated bootstrap diode to eliminate external component count. the resistor commonly placed between mosfet gate and source for discharge is also integrated, making external component minimal. this device combined with upi multi-phase buck pwm controller forms a complete core voltage regulator for advanced microprocessors. the up1965s supports enable/disable function that reduces the power consumption to prolong battery life. both gate drives are turned off by pulling low en pin or high-impedance at pwm pin, preventing rapid output capacitor discharge during system shutdown. this device also supports three pwm input states that along with pwm controller to provide a complete power solution. the up1965s implements anti-shoot-through protection that prevents cross-conduction of the external mosfet while maintains minimum deadtime for optimized efficiency. this device also supports supply input under voltage lockout. the up1965s is available in thermally enhanced wdfn2x2-8l package. ?? ?? ? desktop/laptop cpu/gpu core voltage regulators ?? ?? ? high frequency low profile dc/dc converter ?? ?? ? high current low voltage dc/dc converter pin configuration 8 phase ugate gnd pwm lgate boot en vcc nc 7 6 5 1 2 3 4
up1965s 2 up1965s-ds-f0000, may. 2018 www.upi-semi.com typical application circuit ugate boot phase gnd lgate pwmen vcc pwm input 5v v in v out rc snubber enable input 1 7 2 6 5 8 4 3 functional block diagram boot vcc ugat e phas e en pwm lgate gnd uvlo output disable 44k 44k vcc 44k shoot-through protection shoot-through protection tri-state detect
up1965s 3 up1965s-ds-f0000, may. 2018 www.upi-semi.com .on ni pe man ni pn oitcnufnip 1t oob .ylppus partstoob partstoobehttcennoc.revirdetagreppugnitaolfehtrof croticapac toob .t iucricpartstoobamrofotnipesahpehtdnaniptoobneewteb e kam.tefsomreppuehtnonrutotegrahcehtsedivorproticapa cpartstoobeht ctahterus toob .ciehtraendecalpsi 2m w p .tupnim w p eht.stuptuorevirdehtslortnocdnatupnilevelcigolsevie cernipsiht , hgihsitupninenehw.wolsitupninefietatsecnadepmitupni hgihnisinipm w p r otsisereht.tiucriclanretniybetats-irtotdellupeblliw egatlovnip m w peht e btsum gnittesnoitcnufrellortnoc m w profdng otnip m w p morfdetcennoc k51nahtretaerg . 3n e .lortnocelbane dnaetaguhtobsecrofdnanoitarepolamronselbasidnipsiht n ehw.nip m w pfoetatsehtslortnocoslanipsiht.woldellupsitinehwffo etagl o nsiereht.etatsecnadepmitupni-hgihnisinip m w peht,woldellupsinipneeht .nipsihtotmsinahcem wol-llupropu-lluplanretni 4c cv .ciehtrofegatlovylppus s ihttcennoc.ciehtrofegatlovsaibsedivorpnipsiht .retlifc/rnahtiwtissapybdnaecruosegatlovv5otnip 5e tagl .tuptuorevirdetagrewol s iht.tefsomrewolfoetagehtotnipsihttcennoc e htnehw enimretedotyrtiucricnoitcetorphguorht-toohsehtybder otinom sinip .ffodenrutneebsahtefsomrewol 6d ng .ciehtrofdnuorg .nipsihtottcepserhtiwderusaem eraslevelegatlovlla 7e sahp .edon hctiws esahp dnatefsomreppuehtfoecruosehtotnipsihttcennoc etaguehtrofhtapnruterehtsadesusinipsiht.tefsomrewol ehtfoniardeht o tyrtiucricnoitcetorphguorht-toohsehtybderotinom oslasinipsiht.revird .ffodenrutneebsahtefsomreppuehtnehwenimreted 8e tagu .tuptuorevirdetagreppu s iht.tefsomreppufoetagehtotnipsihttcennoc e htnehw enimretedotyrtiucricnoitcetorphguorht-toohsehtybder otinom sinip .ffodenrutneebsahtefsomreppu dapdesopx ec n .detcennoc yllanretniton t onsis5691pufodapdesopxeehthguohtla d esopxeehttcennocotdednem mocerylhgihllitssiti.dngotdetcennocyllacirtcele .noitapissidtaeh mumixamrofenalpdng otdap functional pin description
up1965s 4 up1965s-ds-f0000, may. 2018 www.upi-semi.com functional description enable control the en pin controls pwm pin state and the mosfet gate driver output state. logic input low to en pin disables the gate drivers. both ugate and lgate will be kept low, and pwm pin will be in high input impedance state. logic input high to en pin enables the gate drivers after a delay time t pdhden as shown in figure 1. during this time period the pwm pin stays at high input impedance state, both ugate and lgate outputs are kept low, and the internal control circuit does not respond to the pwm input voltage. after t pdhden expires, both ugate and lgate begin to respond to the pwm input. this mechanism is specifically designed for upis pwm controller, which uses its pwm pin as a multi-functional pin. pwm lgate ugate en t pdhden figure 1. enable control, en pwm inputthe pwm pin is a tri-state input. logic high turns on the high-side gate driver and turns off the low-side gate driver once the por of vcc is granted and en is kept high. logic low turns off the high-side gate driver and turns on the low-side gate driver. high impedance input at pwm pin will keep both high-side and low-side gate drivers low and turns off both mosfets. the pwm pin voltage is kept around 1.6v by internal bias circuit when floating. refer to figure 1, during t pdhden , both ugate and lgate are kept low, the pwm pin is in high-input impedance state, and the pwm input will be ignored. for the pwm controller uses its pwm pin as a multi-functional pin, a resistor will be connected from pwm pin to gnd to set parameter. note that this resistor must be greater than 15k . lower resistor value will cause incorrect pwm voltage level atthe pwm pin when the pwm controller output is in tri- state (high-impedance state). low-side driverthe low-side driver is designed to drive a ground referenced n-channel mosfet. the bias to the low-side driver is internally connected to vcc supply and gnd. the low- side driver output is out of phase with the pwm input when it is enabled. the low side driver is held low if the en pin is pulled low or high-impedance at pwm pin. high-side driver the high-side driver is designed to drive a floating n-channel mosfet. the bias voltage to the high-side driver is internally connected to boot and phase pins. an integrated bootstrap switch that is connected between boot and vcc pins provides the bias current for the high side gate driver. the bootstrap capacitor c boot is charged to v cc when phase pin is grounded by turning on the low-side mosfet. the phase rises to v in when the high-side mosfet is turned on, forcing the boot pin voltage to v in + v cc that provides voltage to hold the high-side mosfet on. the high-side gate driver output is in phase with the pwm input when it is enabled. the high-side driver is held low if the en pin is pulled low or high-impedance at pwm pin. shoot through protection the shoot-through circuit prevents the high-side and low- side mosfets from being turned on simultaneously and conducting destructive large current. it is done by turning on one mosfet only after the other mosfet is off already with adequate delay time. at the high-side off edge, ugate and phase voltages are monitored for anti-shoot-through protection. the low- side driver will not begin to output high until both (v ugate - v phase ) and v phase are lower than 1.2v, making sure the high-side mosfet is turned off completely. at the low-side off edge, lgate voltage is monitored for anti-shoot-through protection. the high-side driver will not begin to output high until v lgate is lower than 1.2v, making sure the low-side mosfet is turned off completely.
up1965s 5 up1965s-ds-f0000, may. 2018 www.upi-semi.com (note 1) supply input v oltage, vcc ---------------------------------------------------------------------------------------------------- --------- -0.3v to +6v boot to phase --------------------------------------------------------------------------------------------------------------------------- -0.3v to +6v phase to gnd dc ---------------------------------------------------------------------------------------------------------------------------------------- -0.7v to +30v < 200ns ----------------------------------------------------------------------------------------------------------------------------------- -8v to +36v boot to gnd dc ------------------------------------------------------------------------------------------------------------------------------- -0.3v to (vcc +36v) < 200ns -------------------------------------------------------------------------------------------------------------------------------- -0.3v to +42v ugate to phase dc -------------------------------------------------------------------------------------------------------------- -0.3v to (boot - phase +0.3v) < 200ns --------------------------------------------------------------------------------------------------------- -5v to (boot - phase +0.3v) lgate to gnd dc ------------------------------------------------------------------------------------------------------------------------------- -0.3v to (vcc +0.3v) < 200ns -------------------------------------------------------------------------------------------------------------------------- -5v to (vcc +0.3v) pwm -------------------------------------------------------------------------------------------------------------------------------------------- -0.3v to +6v en --------------------------------------------------------------------------------------------------------------------------------------- -0.3v to (vcc +0.3v) storage temperature ra nge ------------------------------------------------------------------------------------------------------------ -65 o c to +150 o c junction temperature --------------------------------------------------------------------------------------------------------- --------------------------- 150 o c lead temperature (soldering, 10 sec) ----------------------------------------------------------------------------------------- ------------------- 260 o c esd rating (note 2) hbm (human body mode) -------------------------------------------------------------------------------------------------------- ------------- 2kv cdm (charged device mode) ---------------------------------------------------------------------------------------------------- ------------- 500v package thermal resistance (note 3) wdfn2x2 - 8l ja --------------------------------------------------------------------------------------------------------------------- 155 o c/w wdfn2x2 - 8l jc ----------------------------------------------------------------------------------------------------------------------- 20 o c/w power dissipation, p d @ t a = 25 o c wdfn2x2 - 8l ------------------------------------------------------------------------------------------------------------------------------------- 0.65w (note 4) operating junction temperature ra nge ------------------------------------------------------------------------------- -40 o c to +125 o c operating ambient temperature ra nge -------------------------------------------------------------------------------- -40 o c to +85 o c supply input voltage, v cc --------------------------------------------------------------------------------------------------------------- 4.5v to 5.5v power stage input voltage, v in ------------------------------------------------------------------------------------------------------- 4.5v to 28v note 1. stresses listed as the above absolute maximum ratings may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. devices are esd sensitive. handling precaution recommended. note 3. ja is measured in the natural convection at t a = 25 o c on a low effective thermal conductivity test board of jedec 51-3 thermal measurement standard. note 4. the device is not guaranteed to function outside its operating conditions. absolute maximum rating thermal information recommended operation conditions
up1965s 6 up1965s-ds-f0000, may. 2018 www.upi-semi.com retemara pl obmy ss noitidnoctse tn i mp y tx a mt inu tupniylppus tnerrucylppu si cc v0=n e- -0 10 2a u dlohserhtgnisir rop cc vv htrcc v cc gnisi r8 . 30 . 44 . 4v siseretsyh rop cc vv syhcc - -2 . 0- -v tupnim w p levelhgihtupn im w p h 9. 2- -- -v levelwoltupn im w p l - -- -4 . 0v egatlovgnitaolf m w pm w p tlf - -6 . 1- -v tnerructupnim w pi mwp v0= m w p0 25 -0 03 -0 02 -a u v3.3= m w p5 . 016 . 1a m v5= m w p1 2 6 . 2a m emitffo-dlohnwodtuhsetats-sirt 0 70 3 10 2 2s n lortnocelbane hgihtupn in e h 2- -- -v woltupn in e l - -- -6 . 0v emityalednoitagaporp t nedhdp 16 0 1s u t nedldp - -- -0 0 6s n edoid partstoob egatlovdrawrof - -3 3. 0- -v revirdedishgih gnicruos,ecnatsisertuptu or crs_h v toob v- esahp i,v5= etagu am08- =- -7 . 04 .1 gniknis,ecnatsisertuptu or kns_h v toob v- esahp i,v5= etagu am08- =- -4 . 08 .0 emitgnisirtuptu ot etagur v toob v- esahp c,v5= daol fn3 =- -0 2- -s n emitgnillaftuptu ot etaguf v toob v- esahp c,v5= daol fn3 =- -0 1- -s n emityalednoitagaporp t guhdp v toob v- esahp v5 =- -0 35 4s n t guldp v toob v- esahp v5 =- -0 20 3s n electrical characteristics (vcc = 5v, t a = 25 o c, unless otherwise specified)
up1965s 7 up1965s-ds-f0000, may. 2018 www.upi-semi.com retemara pl obmy ss noitidnoctse tn i mp y tx a mt inu revirdedis wol gnicruos,ecnatsisertuptu or crs_l v cc i,v5= etagl am08- =- -7 . 04 .1 gniknis,ecnatsisertuptu or kns_l v cc i,v5= etagl am08- =- -3 . 07 .0 emitgnisirtuptu ot etaglr v cc c,v5= daol fn3 =- -0 2- -s n emitgnillaftuptu ot etaglf v cc c,v5= daol fn3 =- -0 1- -s n emityalednoitagaporp t glhdp v cc v5 =- -0 35 4s n t glldp v cc v5 =- -0 20 3s n electrical characteristics en ugate or lgate t pdlden t pdhden 90% 10% pwm t pdllg t pdhlg t pdlug t pdhug t flgate t rugate t fugate t rlgate lgate ugate
up1965s 8 up1965s-ds-f0000, may. 2018 www.upi-semi.com ugate (5v/div) pwm (2v/div) lgate (2v/div) phase (5v/div) ugate-phase (2v/div) ugate (10v/div) pwm (2v/div) lgate (5v/div) ugate (10v/div) pwm (2v/div) lgate (5v/div) ugate (5v/div) pwm (2v/div) lgate (2v/div) phase (5v/div) ugate-phase (2v/div) ugate (5v/div) pwm (2v/div) lgate (2v/div) phase (5v/div) ugate-phase (2v/div) ugate (5v/div) pwm (2v/div) lgate (2v/div) phase (5v/div) ugate-phase (2v/div) ugate falling to lgate rising dead time time : 20ns/div v in =12v, v cc =5v,converter load = 0a, mosfet = qm3816*2ea, rc snubber,r=2.2 ,c=3.3nf typical operation characteristics pwm enter tristate operation time : 10us/div v in =12v, v cc =5v,converter load = 0a, mosfet = qm3816*2ea pwm exit tristate operation lgate falling to ugate rising dead time time : 20ns/div v in =12v, v cc =5v,converter load = 0a, mosfet = qm3816*2ea, rc snubber,r=2.2 ,c=3.3nf lgate falling to ugate rising dead time time : 20ns/div v in =12v, v cc =5v,converter load = 20a, mosfet = qm3816*2ea, rc snubber,r=2.2 ,c=3.3nf ugate falling to lgate rising dead time time : 20ns/div v in =12v, v cc =5v,converter load = 20a, mosfet = qm3816*2ea, rc snubber,r=2.2 ,c=3.3nf time : 10us/div v in =12v, v cc =5v,converter load = 0a, mosfet = qm3816*2ea
up1965s 9 up1965s-ds-f0000, may. 2018 www.upi-semi.com ugate (10v/div) pwm (5v/div) lgate (5v/div) en (5v/div) ugate (10v/div) pwm (5v/div) lgate (5v/div) en (5v/div) ugate (5v/div) pwm (2v/div) lgate (2v/div) phase (5v/div) ugate-phase (2v/div) typical operation characteristics short pulse time : 40ns/div v in =12v, v cc =5v,pwm=30ns,converter load = 0a, mosfet = qm3816*2ea en go high delay time : 20us/div v in =12v, v cc =5v,pwm=300khz,d=5%, mosfet = qm3816*2ea en go low delay time : 20us/div v in =12v, v cc =5v,pwm=300khz,d=5%, mosfet = qm3816*2ea
up1965s 10 up1965s-ds-f0000, may. 2018 www.upi-semi.com package information note 1.package outline unit description: bsc: basic. represents theoretical exact dimension or dimension target min: minimum dimension specified. max: maximum dimension specified. ref: reference. represents dimension for reference use only. this value is not a device specification. typ. typical. provided as a general value. this value is not a device specification. 2.dimensions in millimeters. 3.drawing not to scale. 4.these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15mm. wdfn2x2 - 8l 1 4 5 0.18 - 0.30 0.50 bsc 1.90 - 2.10 1.90 - 2.10 0.50 - 0.80 0.20 - 0.50 1.10 - 1.40 0.00 - 0.05 0.20 ref 0.70 - 0.80 8
up1965s 11 up1965s-ds-f0000, may. 2018 www.upi-semi.com important notice upi and its subsidiaries reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. upi products are sold subject to the taerms and conditions of sale supplied at the time of order acknowledgment. however, no responsibility is assumed by upi or its subsidiaries for its use or application of any product or circuit; nor for any infringements of patents or other rights of third parties which may result from its use or application, including but not limited to any consequential or incidental damages. no upi components are designed, intended or authorized for use in military, aerospace, automotive applications nor in systems for surgical implantation or life-sustaining. no license is granted by implication or otherwise under any patent or patent rights of upi or its subsidiaries. copyright ( c ) 2018, upi semiconductor corp. upi semiconductor corp. headquarter 9f.,no.5, taiyuan 1st st. zhubei city, hsinchu taiwan, r.o.c. tel : 886.3.560.1666 fax : 886.3.560.1888 upi semiconductor corp. sales branch office 12f-5, no. 408, ruiguang rd. neihu district, taipei taiwan, r.o.c. tel : 886.2.8751.2062 fax : 886.2.8751.5064

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